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vhdl project

Open Posted By: highheaven1 Date: 07/01/2021 Graduate Homework Writing

This project needs to be done in 2 weeks

Category: Mathematics & Physics Subjects: Algebra Deadline: 12 Hours Budget: $120 - $180 Pages: 2-3 Pages (Short Assignment)

Attachment 1

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MODİFİED ADDER CİRCUİT- 1 TAM TOPLAYICI=FULL ADDER ELDE GİRİS = CARRY IN ELDE CİKİS = CARRY OUT SECME= SELECTION

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CLASSİC ADDER CİRCUİT

Project Steps (1)

1. VHDL Code of 4 BİT Modified Adder Circuit given in schema, 2. RTL schema of this coded circuit, 3. Simulation for 4 different number values and creating the signal wave(form), 4. Making 8, 16, 32bit versions of the circuit (No RTL Schemas ), 5. Coding 4, 8, 16, 32 bit versions of Classic adder circuit , 6. Every gates delay is assumed to be 1 ns ,

• Modified Adder Circuits Calculation of the maximum delay required for 4, 8, 16, 32 bit versions all Z values to occur.

• Classic Adder Circuits Calculation of the maximum delay required for 4, 8, 16, 32 bit versions all Z values to occur.

• This item will be calculated manually, not a system output!

7. Similar to the report sample given on page 5; • Modified Adder Circuits determination of values of 4, 8, 16, 32 bit versions ‘Maximum

combinational path delay’ . • Classic Adder Circuits determination of values of 4, 8, 16, 32 bit versions ‘Maximum combinational path

delay’ .

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Project Steps (2)

8. Creating Modified and Classic Addition Circuit Comparative Delay Graph for all bit lengths by using the values in 6th step (Excel can be used while creating the graph)

9. Creating Modified and Classic Addition Circuit comparative delay graph for all bit lengths (Excel can be used while creating the graph) By using the values at 7th step

10. Interpretation of both graphs by comparison (interpretation of performance and cost between 2 algorithms)

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Example of Delay Graphic

• Values are not accurate!

7

2,00

4,00

6,00

8,00

1,00

3,00 3,00

1,00

0,00

1,00

2,00

3,00

4,00

5,00

6,00

7,00

8,00

9,00

4 8 16 32

Delay value (ns) mod klasik

PROJECT INCLUDES

• The fallowing contents will be prepared and sent in .zip format. • Source code .vhd file (Not .doc, .txt !)

• Modified Adder Circuit (4, 8, 16, 32 Bit) • Classic Adder Circuit (4, 8, 16, 32 Bit)

• Report .pdf File • Project Cover • 4 Bit Modified Adder Circuit RTL Schema • Simulation Inputs and Signal Waveform for 4 Different Input Values (For 4 bit Modified Adder Circuit) • Project Step 6. calculations (Add photo if you made calculations by handwriting) • Project Step 7 calculations (Add photo if you made calculations by handwriting) • Project Step 8 Graphic • Project Step 9 Graphic • Conclusion and Evaluation ( 1 Paragraph Summarizing the Work Done and Graphic Interpretation)

• REPORT LAYOUT; • Title 16 pt, Writing 12 pt, Times New Roman, Pictures and Graphics Centered, Numbered and explained under

each figure (f.e. Figure 1.1: RTL Schema, Figure 2.1: Simulation Result-1 )

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